‘Key’ 5G building blocks launched by imec

Wim Van Thillo, imec’s programme director for perceptive systems, said: “Our portfolio includes record-breaking A/D converters, reconfigurable low-noise frequency synthesisers, millimetre wave phased array transceivers, antenna modules and more. These building blocks show state-of-the art performance, excel in low-power operation and are low cost by leveraging scaled CMOS technologies.”

The A/D converter, pictured, which has core area of 350 x 325µm, is fabricated using a 16nm CMOS process. Dynamic power consumption is said to be 3.6mW at 300Msample/s, with a signal to noise and distortion ratio of 70.2dB at 204Msample/s.

Meanwhile, the 60GHz RF front-end features eight way calibration-free beamforming to support a large number of antennas. This, says imec, makes it attractive for fixed wireless access and small cell backhaul applications. On-chip transmit-receive switching allows the antenna array to be shared. With an area of 9.6mm2, the chip is targeted at a 28nm CMOS process. Power consumption is said to be 231mW in receive and 508mW in transmit mode.